Implementation of fault-tolerant sequential circuits using programmable logic arrays

An efficient implementation procedure has been developed for the realization of sequential circuits using PLAs. The synthesis procedure is simple and based on a heuristic approach. Synchronous sequential circuits which have been widely used in digital computers over the years can be easily implemented in a single chip layout. One of the major advantages of this method is the reduction in chip area in terms of the fusible links blown to realize the state machine using PLAs