DocumentCode
3335517
Title
A new diagnosis approach for short faults in interconnects
Author
Chao Feng ; Wei Kang Huang ; Lombardi, F.
Author_Institution
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear
1995
fDate
27-30 June 1995
Firstpage
331
Lastpage
339
Abstract
Existing one-step diagnosis approaches for faults in interconnects either yield a long test sequence, or use a non-generalized procedure to generate a shorter test sequence. We propose a new diagnosis approach for short faults in interconnects. The pin-adjacency fault model is assumed. By using a divide-and-conquer strategy, our approach can generate a very compact test vector sequence which can diagnose an unrestricted number of short faults. Our experiments for three benchmarks as well as large random interconnects (up to 50,000 nets) show that our approach can achieve more than 50% savings in the length of the generated test sequence. This can significantly save the diagnosis cost for boundary-scan testing. An adaptive diagnosis approach is further proposed to dynamically truncate the originally generated test sequence based on the current information of faulty nets. The performance of our adaptive approach in terms of the on-line test generation time and the resulting test sequence length is better than for existing adaptive diagnosis approaches when the fault rate is not very small, such as in a new product line. If a low complexity for the ATE is of major importance, then the proposed one-step approach is the best choice.<>
Keywords
adaptive systems; boundary scan testing; computer testing; divide and conquer methods; fault diagnosis; multiprocessor interconnection networks; problem solving; sequences; adaptive diagnosis approach; benchmarks; boundary-scan testing; compact test vector sequence; diagnosis approach; diagnosis cost; divide-and-conquer strategy; dynamic truncation; faulty nets; interconnects; large random interconnects; low complexity; on-line test generation time; one-step approach; performance; pin-adjacency fault model; short faults; test sequence length; Benchmark testing; Chaos; Circuit faults; Computer science; Costs; Fault diagnosis; Integrated circuit interconnections; Packaging; Sequential analysis; Surface-mount technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault-Tolerant Computing, 1995. FTCS-25. Digest of Papers., Twenty-Fifth International Symposium on
Conference_Location
Pasadena, CA, USA
Print_ISBN
0-8186-7079-7
Type
conf
DOI
10.1109/FTCS.1995.466966
Filename
466966
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