Novel digital VLSI GaAs FET circuits for low power and high functional yield

fYear

1991

fDate

1-2 Mar 1991

Firstpage

272

Lastpage

275

Abstract

The complexity of GaAs FET VLSI circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, novel digital GaAs FET circuits are presented that eliminate the DC power dissipation, reduce the area to 50% of that of the conventional static circuit and its larger tolerance to device parameters variations, results in higher functional yield

Keywords

III-V semiconductors; VLSI; digital integrated circuits; field effect integrated circuits; gallium arsenide; integrated logic circuits; D-type flip-flop; FET VLSI circuits; GaAs; HFET process; chip area reduction; digital VLSI; dynamic circuits; high functional yield; low power; maximum power dissipation; Capacitors; Clocks; FET circuits; Gallium arsenide; Integrated circuit noise; Logic circuits; Logic devices; Power dissipation; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1991. Proceedings., First Great Lakes Symposium on

Conference_Location

Kalamazoo, MI

Print_ISBN

0-8186-2170-2

Type

conf

DOI

10.1109/GLSV.1991.143978

Filename

143978

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3335637