DocumentCode
3335908
Title
Design of fail-safe CMOS logic circuits
Author
Bobin, V. ; Whitaker, S.
Author_Institution
Idaho Univ., Moscow, ID, USA
fYear
1991
fDate
1-2 Mar 1991
Firstpage
338
Lastpage
339
Abstract
Design techniques to make CMOS logic circuits fail-safe are reported. The set of transistor stuck-on and stuck-open faults, signal lines stuck-at faults, and bridging faults is partitioned into two classes of faults. Fail-safe property is maintained for multiple faults within a class. Limited fault tolerance capability is introduced as a by-product
Keywords
CMOS integrated circuits; circuit reliability; integrated logic circuits; logic design; CMOS logic circuits; bridging faults; design techniques; fail-safe circuits; fault tolerance capability; multiple faults; signal lines stuck-at faults; stuck-open faults; transistor stuck-on faults; CMOS logic circuits; Circuit faults; Circuit synthesis; Logic circuits; MOSFETs; NASA; Power supplies; Signal design; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-2170-2
Type
conf
DOI
10.1109/GLSV.1991.143993
Filename
143993
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