A 60 nm channel length silicon stacked tunnel transistor

The transistor is a vertical, fully depleted double-gate SOI-MOSFET (silicon-on-insulator metal-oxide-semiconductor-field-effect-transistor) with barriers in the channel region. Gate voltage modulates the internal potential in the intrinsic silicon region and the central shutter barrier or barriers (CSB) also move up and down energetically following the internal potential. The CSB reduce the OFF current substantially, while keeping a high ON current in the device. The role of source and drain barriers is, (1) to adjust the source impedance to the CSB, (2) to act as diffusion barriers keeping a low impurity level within the channel, and (3) to reduce leakage current such as GIDL (gate induced drain leakage) current at the drain side.