Enhanced hole mobilities in tensile-strained Si/sub 1-y/C/sub y/ alloy PMOSFETs

The incorporation of C in Si epitaxial layers can used as an alternative method to deposit tensile-strained Si layers directly on a silicon substrate, for obtaining improved hole transport behavior in the valence band. The proposed method to produce tensile-strained layers is attractive because it eliminates the need to deposit a thick relaxed SiGe buffer layer. Additionally, the elimination of this relaxed buffer layer alloys the concern over dislocations and other defects propagating to the channel region. The fabrication and transport properties of PMOSFETs utilizing a strained-engineered Si/sub 1-y/C/sub y/ channel are reported for the first time in this paper.