Title :
G-vector: a new model for glitch analysis
Author :
Chung, Ki-Seok ; Kim, Tacwhan ; Lin, C.L.
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model
Keywords :
CMOS logic circuits; combinational circuits; logic design; CMOS combinational logic circuits; G-vector model; glitch analysis; glitch elimination; glitch generation; glitch propagation; power consumption; spurious pulses; switching activities; Adders; Ambient intelligence; Frequency locked loops; Logic circuits; Petroleum; Power dissipation; Propagation delay; Switching circuits; Tiles;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806495