• DocumentCode
    3339282
  • Title

    Integrated thermal modeling of heterogeneous eCubes stacked devices

  • Author

    Janczyk, G. ; Bieniek, T. ; Grabiec, P. ; Szynka, J.

  • Author_Institution
    Inst. of Electron Technol., Warsaw
  • fYear
    2008
  • fDate
    24-26 Sept. 2008
  • Firstpage
    80
  • Lastpage
    84
  • Abstract
    Vertical chip integration applied in heterogeneous systems is a design approach used to extend the device functionality and improve its performance. Apart from the design advancements, thermal budget of the device is constrained internal structure of the device. Internal module components limit the efficiency of device cooling. It is one of the most important concerns of vertical integration reliability. Development of vertically integrated devices requires cooperation of different partners and designers. This paper presents thermo-mechanical simulation needs and capabilities. The presented HDL approach is used for thermal modeling of the structure and high level, NDA-proof thermal simulations of modules of stacked, heterogeneous devices.
  • Keywords
    cooling; hardware description languages; integrated circuit design; HDL approach; NDA-proof thermal simulations; constrained internal structure; device cooling; heterogeneous eCubes stacked devices; internal module components limit; thermal modeling; thermo-mechanical simulation; vertical chip integration; Conducting materials; Hardware design languages; Libraries; Mathematical model; Packaging; Semiconductor device modeling; Shape; Temperature; Thermal conductivity; Visualization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Thermal Inveatigation of ICs and Systems, 2008. THERMINIC 2008. 14th International Workshop on
  • Conference_Location
    Rome
  • Print_ISBN
    978-1-4244-3365-0
  • Electronic_ISBN
    978-2-35500-008-9
  • Type

    conf

  • DOI
    10.1109/THERMINIC.2008.4669883
  • Filename
    4669883