Flow for phase locked loop mixed signal simulation and characterization using behavioral modeling

Author

Abdennadher, Salem

Author_Institution

Intel Corp., Sacramento, CA, USA

fYear

2003

fDate

23-25 Feb. 2003

Firstpage

66

Lastpage

70

Abstract

In order to reduce the number of design iterations for complex mixed signal telecommunication ICs, prediction of noise at an early stage of a design is essential. This paper present a robust mixed signal design flow to model phase noise or jitter on a VCO based PLL circuit using a mixed signal hardware description language VHDL-AMS and to measure this jitter.

Keywords

circuit simulation; hardware description languages; integrated circuit design; integrated circuit modelling; integrated circuit noise; jitter; mixed analogue-digital integrated circuits; phase locked loops; phase noise; voltage-controlled oscillators; PLL characterization; PLL mixed signal simulation; VCO; VHDL-AMS; behavioral modeling; complex mixed signal telecommunication IC; design iteration reduction; hardware description language; jitter; noise prediction; phase locked loop; phase noise; Circuit noise; Fluid flow measurement; Hardware design languages; Jitter; Noise reduction; Noise robustness; Phase locked loops; Phase noise; Signal design; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2003. Southwest Symposium on

Print_ISBN

0-7803-7778-8

Type

conf

DOI

10.1109/SSMSD.2003.1190398

Filename

1190398