Phase interpolator using delay locked loop [multiphase clock generation]

Multiphase clocks can ease the clock speed constraints to achieve higher operating speeds. This paper describes a new technique that doubles the phase resolution of a conventional multiphase clock generator composed of multiple delay units. This technique has the additional advantage of using simple building blocks that do not need any kind of sophisticated functions. The fabricated test chip shows that the proposed concept works correctly and, as a typical example, 10-phase clocks with 220 MHz frequency are interpolated to 20-phase clocks with about 10 ps-rms jitter performance.