Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications

A novel logic family called race-free CMOS pass-gate charge recycling logic (FCPCL) has been proposed and analyzed. FCPCL consumes less power with less delay compared to previously reported logic families based on charge recycling. It has the additional benefit of having no sensitivity to signal skew. Using a new regenerator in FCPCL leads to complete elimination of the controller in the circuit, hence the number of transistors was greatly reduced. Considerable improvements in the parameters are proven by simulating a two input NAND gate and a full adder.