Mixed test structure for soft and hard defect detection

Author

Rigaud, F. ; Portal, J.M. ; Aziza, H. ; Nee, D. ; Vast, J. ; Argoud, F. ; Borot, B.

Author_Institution

IM2NP - Inst. Mater. Microelectron. Nanosci. de Provence de Provence, IMT-Technopole de Chateau, Marseille

fYear

2008

fDate

24-27 March 2008

Firstpage

52

Lastpage

55

Abstract

The objective of this paper is to present a mixed test structure designed to characterize yield losses due to hard defect and back-end process variation (PV) at die and wafer level. A brief overview of the structure, designed in a ST-Microelectronics´ 130 nm technology, is given. This structure is based on a SRAM memory array for detecting hard defects. Moreover each memory cell can be configured in the ring oscillator (RO) mode for back-end PV´s characterization. The structure is tested in both modes (SRAM, RO) using a single test flow. Experimental results are given and confirm the ability of the structure to monitor PV and defect density.

Keywords

SRAM chips; nanoelectronics; oscillators; SRAM memory array; ST-Microelectronics; back-end process variation; die level; hard defect detection; mixed test structure; ring oscillator mode; soft defect detection; yield losses; CMOS technology; Circuit testing; Frequency; Integrated circuit interconnections; Inverters; Microelectronics; Random access memory; Registers; Ring oscillators; Vehicle detection;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on

Conference_Location

Edinburgh

Print_ISBN

978-1-4244-1800-8

Electronic_ISBN

978-1-4244-1801-5

Type

conf

DOI

10.1109/ICMTS.2008.4509313

Filename

4509313