DocumentCode
3340643
Title
Highly automated test chip layout and test plan development for parametric electrical test
Author
Gabrys, Ann ; Greig, Wends ; West, Andrew J. ; Lindorfer, Philipp ; French, William
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA
fYear
2008
fDate
24-27 March 2008
Firstpage
96
Lastpage
100
Abstract
This work outlines a fully integrated device development procedure that automates test chip development, including placement and routing algorithms, and electrical test program generation. This procedure improves over classic test chip and electrical test program development by reducing the development timeline and allowing more complete and elegant experimental device design, as well as eliminating many of the opportunities for human error while maximizing reuse between technologies.
Keywords
automatic testing; integrated circuit layout; integrated circuit testing; electrical test program generation; fully integrated device development; highly automated test chip layout; parametric electrical test; placement algorithm; routing algorithm; test plan development; Automatic testing; Microelectronics;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on
Conference_Location
Edinburgh
Print_ISBN
978-1-4244-1800-8
Electronic_ISBN
978-1-4244-1801-5
Type
conf
DOI
10.1109/ICMTS.2008.4509321
Filename
4509321
Link To Document