PLATO P: PLA timing optimization by partitioning

This paper addresses the problem of partitioning a large PLA into a number of smaller PLA´s (sub-PLA´s) such that the total area of these sub-PLA´s is minimum and the cycle time of the partitioned circuit is minimized. First, we describe an iterative improvement method that deals with the case that sub-PLA´s assume arbitrary sizes. Second, we present a partitioning technique based on fuzzy logic that deals with the case that the sizes of the sub-PLA´s are fixed. Finally, we describe a method that considers not only delay through each sub-PLA, but also loading of sub-PLA´s on the stage that is driving them. These techniques have been implemented and significantly outperformed conventional PLA partitioning schemes