A pipelined bit-serial complex multiplier using distributed arithmetic

The design of efficient structure for pipelined bit-serial multiplication of complex numbers using distributed arithmetic under the condition of equal word length for both operands is presented. Equal word length operands can give maximum computation precision when the constraint for communication capability has been set, as in many realistic signal processors. With a different treatment of the residue error of the offset binary representation, the proposed structure has better AT² performance compared with existing approach. It also enables “safe” rounding and presents an exact two word length latency. Finally, multiple level logic optimization is applied in each of the building blocks, showing that there still can be significant improvement even on the so called “well-structured” designs