DocumentCode :
3348941
Title :
An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols
Author :
Vernon, Mary K. ; Lazowska, Edward D. ; Zahorjan, J.
Author_Institution :
Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
fYear :
1988
fDate :
30 May-2 Jun 1988
Firstpage :
308
Lastpage :
315
Abstract :
A family of dynamic cache-consistency-protocols for shared-bus multiprocessor systems is considered. A modeling approach, based on the specification and the iterative solution of sets of equations that express the mean values of interesting performance measures in terms of the mean values of certain model inputs, is presented. The equations are intuitive, in the sense that each can be explained simply in terms of the mechanics of the architecture being modeled. The solution technique is extremely efficient, requiring on the order of one second of CPU time for systems of arbitrary size. This makes it possible to explore a large design space quickly and interactively. The results are essentially as accurate as those of the previously existing techniques, which took hours on I-MIPS processors
Keywords :
buffer storage; parallel architectures; performance evaluation; protocols; storage management; dynamic cache-consistency-protocols; efficient performance analysis technique; iterative solution; multiprocessor snooping cache-consistency protocols; performance measures; shared-bus multiprocessor systems; specification; Analytical models; Communication system traffic control; Computational modeling; Computer science; Equations; Interference; Iterative methods; Multiprocessing systems; Multiprocessor interconnection; Performance analysis; Protocols; Steady-state;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-8186-0861-7
Type :
conf
DOI :
10.1109/ISCA.1988.5241
Filename :
5241
Link To Document :
بازگشت