Hardware Emulation for Real-Time Power System Simulation

The classical approach used to implement digital real-time power system simulators (DRTPSS) consists in modeling the power system network and devices in software, and using numerical integration techniques and parallel processors to solve the resulting equations. This approach has many advantages, but it is subjected to the processor-memory hardware paradigm and the inter-processor communication overhead. The latter imposes a minimum time step that cannot be much decreased even when using higher performance processors. Typically, the minimum time step reported in the literature is around 20 mus. This paper presents a new approach to design and implement high-performance DRTPSS that consists in modeling the power system network and devices directly in VLSI hardware. The network topology and device models are described in a hardware description language (HDL) and mapped to a programmable device (FPGA) by using automatic synthesis tools. The simulation runs directly in hardware resulting in very short simulation time steps. Indeed, the initial results obtained and presented in this work show that time steps in the order of microseconds are possible