Behavioral VHDL transistor slope models

Author

Dube, John ; Navabi, Zainalabedin

Author_Institution

Viewlogic Systems Inc., Malboro, MA, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38078

Abstract

Behavioral CMOS transistor models that can accurately predict the timing and logic operation of a custom designed circuit layout are presented. A simple layout extraction program translates the layout netlist to a transistor level VHDL architecture which can be directly simulated, either as a standalone component or as a system module. Simple VHDL constructs and existing delay models were used to develop the transistor models that provide the design engineer with accurate circuit timing and logic information for simulation with higher level models

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit layout CAD; integrated logic circuits; semiconductor device models; specification languages; CMOS; VHDL constructs; circuit timing; custom designed circuit layout; delay models; higher level models; layout extraction program; layout netlist; logic information; logic operation; simulation; timing prediction; transistor level VHDL architecture; transistor models; CMOS logic circuits; Capacitance; Circuit simulation; Design engineering; Hardware design languages; Logic design; Propagation delay; Semiconductor device modeling; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242930

Filename

242930