1-micron ASIC technology achieves greater than 4000 volts electrostatic discharge protection

Author

Sicz, Ken

Author_Institution

VLSI Technology Inc., Tempe, AZ, USA

fYear

1991

fDate

23-27 Sep 1991

Lastpage

38139

Abstract

Sources of electrostatic discharge (ESD) are many. They include differences in triboelectric charge from dissimilar materials, atmospheric charges resulting from temperature gradients or electric/magnetic fields. ESD levels of thousands of volts can result and cause catastrophic device damage either during device manufacturing or at system- or board-level handling and testing. Circuit design considerations for CMOS I/O structures as well as good ESD handling procedures are required to control ESD damage and provide ESD immunity to greater than 4000 volts

Keywords

CMOS integrated circuits; application specific integrated circuits; electrostatic discharge; integrated circuit technology; integrated circuit testing; 1 micron; 4 kV; ASIC technology; CMOS; ESD handling procedures; ESD immunity; ESD protection; I/O structures; MIL-M-38510; atmospheric charges; board-level handling; circuit design considerations; device manufacturing; electrostatic discharge protection; system level handling; triboelectric charge; Application specific integrated circuits; Biological system modeling; Calibration; Capacitors; Circuit testing; Electrostatic discharge; Manufacturing; Pins; Protection; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0101-3

Type

conf

DOI

10.1109/ASIC.1991.242941

Filename

242941