A Memory Access Scheduling Method for Multi-core Processor

It is well known fact that multi-core processor architecture is the mainstream of the next-generation microprocessor architecture and actualizes by chip multi-core processors (CMP). As the number of cores per processor and the number of threaded applications increase, the performance of more and more applications will be limited by the processor´s memory bandwidth. DRAM memory is a major resource shared among cores in a CMP system. However, shared hardware resources pose a significant resource management problem in designing CMP systems. DRAM bandwidth becomes a critical shared resource makes developers are faced with the challenges of memory wall. The on-chip and off-chip cache or memory resources are limited and in many situations, cannot hold the working set of the threads running on all these cores. Existing DRAM access management schemes provide support for enforcing bandwidth shares but have problems like starvation, complexity, and unpredictable DRAM access latency. In this paper, we analyze the structures of DRAM and the prevalent multi-core architectures, and then we propose a Fair Dynamic Pipelining (FDP) memory access scheduling to resolve the memory wall problem. The experiment result shown that FDP avoids unexpected long latencies or starvation of memory requests using the dynamic pipeline arrangement policy and it provides an alterable priority strategy to make the response of memory more fairly. So that the FDP scheduling makes the bandwidth shares to achieve desired average latencies for multi cores memory accesses.