Design and optimization of a high PSRR CMOS bandgap voltage reference

A structures design methodology to minimize the area and power dissipation in bandgap voltage reference is presented. In this approach, basic equations of the bandgap core besides the area and power estimations and the offset effect are included to extract the optimum bias condition and the size of devices for minimum possible area and power in an acceptable performance. Based on the proposed methodology, a bandgap circuit in a 0.5μm CMOS technology is fabricated which realizes a temperature coefficient of 20 ppm/°C and a standard deviation of 9.4mV without trimming. The entire circuit consumes 160μA and the silicon area is 0.085mm². Measurements on 240 samples show a good agreement with simulations.