Soft decoder architecture of LT codes

Luby transform (LT) codes, as the first class of efficient rateless codes, attract a lot of attention in the coding theory field. However, the VLSI implementation of LT codes is challenging due to its random code construction characteristic as well as the flexible output length. In this paper, we present an applicable architecture of a soft-decision LT decoder with a block length of 1024 bits and 100 iterations. Partly parallel input node processing and output node processing techniques are both adopted to accelerate decoding speed. An efficient router and reverse router are designed to indicate the graphic connectivity between input nodes and output nodes. The parallel architecture is prototyped on the target FPGA device.