Low-complexity high-speed 4-D TCM decoder

Author

He, Jinjin ; Wang, Zhongfeng ; Liu, Huaping

Author_Institution

Sch. of EECS, Oregon State Univ., Corvallis, OR

fYear

2008

fDate

8-10 Oct. 2008

Firstpage

216

Lastpage

220

Abstract

This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture for the transition metrics unit (TMU) is proposed to significantly reduce the computation complexity without degrading the performance. In addition, pipelining and parallel processing techniques are exploited to increase the decoding throughput. Synthesis results show that the FPGA implementation of the TCM decoder can achieve a maximum throughput of 1.062 Gbps.

Keywords

field programmable gate arrays; phase shift keying; trellis coded modulation; FPQA; high-speed phase shift keying trellis coded modulation; low-complexity 4-dimensional 8-ary trellis coded modulation; parallel processing techniques; transition metrics unit; Computer architecture; Decoding; Degradation; Field programmable gate arrays; Modulation coding; Parallel processing; Phase modulation; Phase shift keying; Pipeline processing; Throughput; FPGA; Trellis coded modulation; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2008. SiPS 2008. IEEE Workshop on

Conference_Location

Washington, DC

ISSN

1520-6130

Print_ISBN

978-1-4244-2923-3

Electronic_ISBN

1520-6130

Type

conf

DOI

10.1109/SIPS.2008.4671765

Filename

4671765