Microprocessor modeling in VHDL without a gate/RTL/behavioral model of the microprocessor

A microprocessor model is discussed that has a behavioural model for the software functionality and an I/O interface to communicate with the hardware models. It is not a true microprocessor model executing real code from ROM, but can be thought of as a socket-replacement model. This model acts similarly to a real microprocessor model with its associated ROM and RAM. It has several advantages over a real microprocessor model with ROM and RAM. There is no need for simulator support of a high level language source debugger, the runtime needed to execute the model is much shorter (especially if the real microprocessor model cannot run on an accelerator), and the software does not need to be as far along in the design cycle because there is no need for the microprocessor compiled code. The implementation issues involved with this kind of microprocessor model are discussed, including the use of entities and processes, the use of wait statements and signals, interfacing with hardware models, enforcing timing, and dealing with asynchronous microprocessor signals