Monte Carlo simulation of low voltage hot carrier effects in non volatile memory cells

Recent experiments on MOSFETs and non-volatile memory cells indicated a non-trivial bias and temperature dependence of substrate (I/sub B/) and gate (I/sub G/) currents whenever the drain voltage (V/sub DS/) becomes comparable to the critical values corresponding to the band gap, and the Si-SiO/sub 2/ barrier energies. In this paper, these experiments are analyzed by means of detailed Monte Carlo simulations. The role played by electron-electron scattering (EES), impact ionization feedback (IIF), band gap variations with temperature (/spl Delta/E/sub G/) and tunneling through the barrier in explaining the experimental results is pointed out.