Base structures of the high performance multichannel encryption processors

In this work the basic structure of a processor that performs multichannel data processing by the symmetric block data encryption algorithms (SBDEA) is proposed. Attention is concentrated on the following issues: (1) the basic structure of the multichannel data encryption processor using SBDEA that process the data in all standard modes of operation; (2) the basic structure of the single-functional processors that perform data encryption and decryption in all modes of operation; (3) the basic structure of single-functional processors that are oriented on the either data encryption or decryption in all modes of operation. Analysis and comparison of above mentioned structures of multichannel processor are made. As the criteria for structure comparison the hardware costs for the processor implementation and the performance were taken. Three variables of the multichannel processor structure-the iterative, the pipelined, and the iterative-pipelined are proposed. It is demonstrated that for ensuring high performance the most effective are the multifunctional pipelined processor and the iterative-pipelined processor