• DocumentCode
    3357335
  • Title

    A decomposed hierarchical logarithmic scheduling algorithm for input-queued switches

  • Author

    Bidoki, Ali Mohammad Zareh ; Azhari, Sayed Vahid ; Yazdani, Nasser

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
  • Volume
    2
  • fYear
    2003
  • fDate
    23 Feb.-1 March 2003
  • Firstpage
    1662
  • Abstract
    Throughput of input queued switches is limited to 58.6% due to head of line blocking (HoL). Using virtual output queuing (VOQ) at inputs and a proper scheduling algorithm, near 100% throughput can be achieved. Scaling in terms of number of ports and line rate is an important factor for high-speed switches. Current available switches support line rates about 10 Gbps, which is due to their slow schedulers. A novel schedule called DHL, which is at least 2 times faster than schedulers like iSLIP, is proposed. The scheduler can be used to build very high capacity switches and support data rate up to 20 Gbps while performing better for bursty and IP traffic. The scheduler´s speed can be increased 2 times by pipelining. A synthesis of the scheduler is given and its area and delay for different number of switch sizes are provided. DHL scales well in terms of performance, area and delay. Its area and delay scale linear and logarithmic with the number of input ports, respectively, while its performance remains quite the same. The scheduler can be implemented with low complexity for many service policies. Simulation results regarding the average delay, throughput, burst reduction and fairness with respect to the switch size are reported.
  • Keywords
    queueing theory; scheduling; telecommunication switching; 10 Gbit/s; 20 Gbit/s; DHL scheduler; HoL; IP traffic; VOQ; burst reduction; bursty traffic; decomposed hierarchical logarithmic scheduler; head on line blocking; high-speed switches; iSLIP; input-queued switches; pipelining; round robin policy; scheduling algorithm; shared memory switches; throughput; virtual output queuing; Bandwidth; Binary trees; Delay lines; Marketing and sales; Pipeline processing; Scheduling algorithm; Switches; Telecommunication traffic; Throughput; Traffic control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Telecommunications, 2003. ICT 2003. 10th International Conference on
  • Print_ISBN
    0-7803-7661-7
  • Type

    conf

  • DOI
    10.1109/ICTEL.2003.1191683
  • Filename
    1191683