VLSI design exchange with intellectual property protection in FPGA environment using both secret and public-key cryptography

With the advent of multi-million gate chips, field programmable gate arrays (FPGAs) have achieved high usability for design verification, exchange, test and even production. Adding to this is the possibility of reusing readily available licensed IP to shorten the design cycle. A major concern for IP owners is the possible over-deployment of the IP into more devices than originally licensed. In this paper, we propose a system based on both public-key and secret-key cryptography embedded in a secured design exchange protocol for protecting the rights of the IP owner. The system consists of hardware-supported design encryption and secured device authentication protocols. Design encryption based on secured device identification ensures that the IP can only be deployed into explicitly identified and agreed upon devices. The system uses a combination of secret and public-key cryptographic functions devised for an uncomplicated trustable design exchange scenario. The public-key functions use modular squaring (Rabin lock) on the FPGA chip instead of exponentiation to reduce the hardware complexity.