Title :
Using all signed-digit representations to design single integer multipliers using subexpression elimination
Author :
Dempster, A.G. ; Macleod, M.D.
Author_Institution :
Westminster Univ., London, UK
Abstract :
A new algorithm is introduced for design of integer multipliers using subexpression elimination. Hartley´s algorithm for subexpression elimination is applied to all possible signed-digit representations of the integer. Results are within 1% of the slow optimal exhaustive searches for 19-bit integers.
Keywords :
digital arithmetic; digital filters; multiplying circuits; Hartley algorithm; signed-digit representations; single integer multipliers; subexpression elimination; Adders; Algorithm design and analysis; Circuits; Finite impulse response filter; Software algorithms; Software performance; Topology; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328709
