Commentary: Trends, Challenges and Opportunities in Semiconductor Memory Technology Scaling

As IC dimensions continue to shrink into the nanometer realm, conventional CMOS scaling appears to be running up against thermal and physical scaling wall. Technology innovations that can circumvent these scaling limits are required in order to achieve the performance gains needed to support the market demands. These performance requirements are driving the introduction of new materials and devices architectures in the process flow. In addition, the aspect ratio of nanostructures is increasing since the vertical dimension of the nano scale device structures in many instances, does not shrink. These high aspect ratio nanostructures pose a variety of new challenges related to patterning, deposition, and cleaning processes, and for the mechanical stability during and after fabrication. Nanotechnology is driving developments of materials with unique physical and chemical characteristics. These materials can potentially help extend the scaling of CMOS based semiconductor devices for logic and memory applications. For memory, conventional charge based concepts may be reaching fundamental limits and new concepts need to be explored.