Effect of glitches on the efficiency of components´ region-constrained placement as a fast approach to reduce FPGA´s dynamic power consumption

The effect of components´ region-constrained placement on reducing internal nets total capacitance and the corresponding change in internal nets´ total dynamic power consumption is investigated. Two logic circuits were specified as components covering around 80% of total FPGA busy gates. These components are multiplexers and adders along with multipliers. Each of these components was implemented on two of Xilinx FPGA´s families, namely; Spartan II and Virtex. Gate-level power estimation for different region-constrained placements of each logic circuit was carried out using the Xilinx hierarchal power distribution analyzer, XFower