A new protocol stack model for network on chip

Author

Dehyadgari, M. ; Nickray, M. ; Afzali-Kusha, Ali ; Navabi, Z.

Author_Institution

Sch. of Electr. & Comput. Eng., Tehran Univ.

fYear

2006

fDate

2-3 March 2006

Abstract

In this paper, we present a communication protocol for network on chip architectures which have complex packet switched communication protocols. In order to manage this complexity and advance reusability, a layered approach is taken. It is a 4-layered protocol stack including application, transaction, data-link and physical layers. Our protocol stack supports the best effort traffic as well as guaranteed bandwidth using the virtual channels which logically share the physical links. In order to evaluate the design, an HDL implementation of this protocol stack is implemented and synthesized. The results show 0.5% of a Virtex II 2VP30 FPGA is employed by our proposed protocol stack for each resource network interface

Keywords

field programmable gate arrays; hardware description languages; network-on-chip; packet switching; protocols; telecommunication traffic; 4-layered protocol stack; HDL implementation; Virtex II 2VP30 FPGA; communication protocol; complex communication protocols; network interface; network on chip architectures; packet communication protocols; protocol stack model; switched communication protocols; virtual channels; Bandwidth; Communication switching; Field programmable gate arrays; Hardware design languages; Network synthesis; Network-on-a-chip; Packet switching; Physical layer; Protocols; Telecommunication traffic;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on

Conference_Location

Karlsruhe

Print_ISBN

0-7695-2533-4

Type

conf

DOI

10.1109/ISVLSI.2006.7

Filename

1602486