Testing of UltraSPARC T1 Microprocessor and its Challenges

Author

Tan, P.J. ; Le, Tung ; Ng, Keng-Hian ; Mantri, Prasad ; Westfall, James

Author_Institution

Sun Microsyst. Inc., Sunnyvale, CA

fYear

2006

fDate

Oct. 2006

Firstpage

1

Lastpage

10

Abstract

This paper presents the testing methodology of the UltraSPARC T1 microprocessor and the challenges to productizing the industry´s first 8 cores and 32 thread microprocessor. The challenges include effectively testing 8 individual cores that share common functional blocks (L2 cache, cache crossbar, floating point unit), reducing 8times conventional production test time and tester memory while achieving the same coverage, and productizing 6 core or 8 core devices at the targeted frequency. Highlights of DFT features designed to overcome the challenges are presented followed by a production flow together with key learning and future improvement plans

Keywords

cache storage; design for testability; floating point arithmetic; logic testing; microprocessor chips; 6 core devices; 8 core devices; DFT; L2 cache; UltraSPARC T1 microprocessor testing; cache crossbar; common functional blocks; design for testability; floating point unit; Control systems; Design for testability; Frequency; Microprocessors; Production; Random access memory; Read-write memory; Sun; System testing; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2006. ITC '06. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

1-4244-0292-1

Electronic_ISBN

1089-3539

Type

conf

DOI

10.1109/TEST.2006.297637

Filename

4079315