A high-speed, low-power 3D-SRAM architecture

This paper presents a novel 3D-SRAM architecture that can be used to extend the scaling of SRAM. This architecture significantly reduces the bit-line capacitance, achieves 3.4 times reduction in active power consumption and 1.8 times reduction in access time. In this architecture, local bit-lines are vertical and connect through select transistors to the global bit-lines routed on the bottom level. A proof-of-concept 32Kb sub-array emulating the critical path of the 3D-SRAM has demonstrated about 5 times improvement in power-delay over conventional 2D-SRAM.