Survey of test strategies for System-on Chip and it´s embedded memories

Today´s submicron VLSI technology has been emerged as integration of many VLSI ICs into a single Si Chip called System-on-Chip (SoC). The SoC architecture normally contains multiple processors along with either separate or centralized memory blocks as its core elements as well as many noncore elements, e.g., Cache/DRAM controllers, I/O Controllers. Due to the increased demands for high data storage, the integration of on-chip memories ranging from Gigabytes to Terrabytes is becoming essential for the latest SoC technology. To improve the reliability and performance of SoCs due to technology miniaturization and increased memory density, there is a need to incorporate on-chip self-testing unit for testing these memory units. Further, to improve the yield and fault tolerance of on-chip memories without degradation on its performance, self repair mechanism may be integrated on chip. Apart from memory self test and repair., another biggest challenge in SoC testing is the testing of logic blocks (core elements) as well as the noncore elements as specified earlier. This paper brings out the reviews of BIST strategies from various literatures that are being applied for testing of embedded memories and IP cores along with associated noncore elements.