A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer

A 65 nm HDMI TX PHY was designed with supply-regulated dual-tuning PLL and blending multiplexer. The proposed PLL uses a new dual-tuning scheme for small capacitor and low-jitter while keeping the supply regulation capability. A fractional-N operation for non-integer pixel clock generation was implemented with a blending multiplexer which enables seamless switching of high-speed multiphase clock. The fabricated PHY gives maximum 3.4 Gbps data rate per channel and shows 34 ps peak-to-peak data jitter.