Efficient Latch and Clock Structures for System-on-Chip Test Flexibility

This paper describes a novel implementation of edge-triggered flip-flops that incorporates the most optimum features of the leading design-for-testability (DFT) methods in the industry in a manner that is efficient from the standpoint of performance, power and area. The result is a flip-flop design that provides testability that is free of timing hazards (race-free and LSSD compatible), while operating at product frequency using only a single edge clock