Characterization, simulation, and modeling of FET source/drain diffusion resistance

We present an innovative and comprehensive approach to characterize and model FET source/drain diffusion resistance. We present a set of new SPICE models for the parasitic resistance in FET source and drain regions. Our FET source/drain diffusion resistance model has been verified with field solver simulation results, and is found to be very accurate over a wide range of parameter values. We also present a set of micro testing structures to measure and characterize diffusion resistance. This approach has been validated using hardware data from a 65 nm SOI technology.