Exact At-speed Delay Fault Grading in Sequential Circuits

This paper examines the problem of exact delay fault grading in non-scan sequential circuits using a sequence of test patterns that are applied with a rated clock. Delay faults ending at flip-flops are latched as uncorrelated errors. The errors latched on flip-flops by previous tests may enhance the at-speed delay fault coverage for each pattern in the sequence. In addition, the propagation of errors (and the faults they represent) may be facilitated by other latched errors as well as potential delayed transitions activated by each at-speed test application. An exact grading method is presented and its impact over existing methods is demonstrated experimentally