A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise

As one way of reducing the reliance on mixed signal testers for circuits with small analog content, researchers have proposed built-in self-test (BiST) techniques that target specific parameters of analog circuits. Most BiST techniques for phase locked loops (PLL) aim at measuring the timing jitter through precise on-chip clocks and/or additional computation of measured specs. In this paper, we propose a built-in test circuit to perform go/no-go testing for in-band PLL phase noise. Our circuit measures the band-limited, low frequency noise power at the input of the voltage controlled oscillator (VCO) which is translated as the high frequency phase noise at the output of the PLL. Our circuit contains a self calibration sequence based on a simple sinusoidal input to make it robust to process variations. The circuit is implemented using 0.8mum CMOS process with the equivalent area of roughly 800 2-input minimum size NAND gates. Monte Carlo simulations have confirmed that the test circuit can robustly detect noise levels that are above the specified fail level