Performance of Full Adder with Skewed Logic

In combinational circuit skewed gates are very attractive along the critical paths to improve delay as well as leakage current of certain design. Conventional static un-skew CMOS network will not favor the outputs to switch in certain direction like high or low. However, skewed logic gates in static CMOS network can favor a certain direction because each gate is guaranteed to solely make only a pull-up or a pull-down transition to increase performances and driving capabilities of the transistor. In this paper, we propose 4 different full adder circuits with skewed and un-skewed logic style and its comparison is made. It is observed that circuit with skewed logic style achieves high performance and less delay when compared to normal skew CMOS circuit. The delay calculation for these full adder circuits are estimated using logical effort method.