• DocumentCode
    3361271
  • Title

    A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR

  • Author

    Erba, S. ; Pozzoni, M. ; Pisati, M. ; Brama, R. ; Sanzogni, D. ; Depaoli, E. ; Viola, P. ; Svelto, F.

  • Author_Institution
    STMicrolectron., Pavia
  • fYear
    2008
  • fDate
    21-24 Sept. 2008
  • Firstpage
    559
  • Lastpage
    562
  • Abstract
    A 65 nm CMOS receiver including a tapered chain linear equalization and a mixer based clock recovery circuit capable of SSC tracking is presented. The proposed architecture works up to 10 Gb/s with transmission channels with more than 20 dB loss at Nyquist, while consuming 110 mA and occupying 0.25 mm2.
  • Keywords
    CMOS integrated circuits; clocks; equalisers; CMOS receiver; Nyquist loss; bit rate 10 Gbit/s; linear backplane equalization; mixer-based self-aligned CDR; size 65 nm; transmission channels; Backplanes; Clocks; Decision feedback equalizers; Delay; Integrated circuit interconnections; Interference; Optical signal processing; Phase locked loops; Propagation losses; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2018-6
  • Electronic_ISBN
    978-1-4244-2019-3
  • Type

    conf

  • DOI
    10.1109/CICC.2008.4672146
  • Filename
    4672146
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3361271