Title :
Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS
Author :
Ikeda, Makoto ; Ishii, Ken ; Sogabe, Taku ; Asada, Kunihiro
Author_Institution :
Univ. of Tokyo, Tokyo
Abstract :
This paper presents measurement results on datapath delay distributions for data/instruction against Process, Voltage and Temperature (PVT) variations in 90nm CMOS. Datapath delay has been measured using a completion signal generated at the end of datapaths with dual-rail logic according to data and instructions comprehensively for multiple Vdd and Temperature among several chips to show PVT variations. Measurement results were compared with the equivalent design in 0.35um and demonstrated that the average delay variation against PVT variation was 16% for 90nm where that was 10% for 0.35um CMOS.
Keywords :
CMOS integrated circuits; delay circuits; CMOS; PVT variations; Process Voltage Temperature variations; data/instruction; datapath delay distributions; delay variation; dual-rail logic; multiple Vdd; size 0.35 mum; CMOS logic circuits; CMOS process; Delay estimation; Dynamic voltage scaling; Microprocessors; Semiconductor device measurement; Signal design; Signal generators; Switches; Timing;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4510953
