Abstract :
With the advent of System-on-Chip (SoC) technology and integration of multiple cores on a single die resulting in Multi-Core chips, complexity of integrated circuits has compounded. This has resulted in additional complexity in debugging Silicon after manufacturing. With some of the SoCs and MultiCores integrating analog cores, the task of debugging deeply embedded analog cores is becoming even more a difficult task. For faster time to market, SoCs and MultiCores instantiate reuse cores. Reuse cores could be soft-cores or hard-cores, sometimes developed internally within the same organization or cores procured externally from external vendors. Design for Debug needs to be planned right from the beginning while developing the reuse cores for ease of debug at the SoC as well as at the MultiCore level, in order to avoid challenges related to Silicon Debug. This panel will address the issue related to "Are these debug features that are incorporated in reuse cores sufficient for SoCs and MultiCores that are being designed today?"
