Model order reduction of on-chip interconnects

In this paper, we describe a methodology for the efficient extraction and model order reduction of large on-chip interconnects. We propose a methodology that results in simulation time reduction by at least an order of magnitude, compared to commercial model order reduction software, by adopting frequency domain vector fitting to reduce the number of poles required to represent the interconnect. The proposed methodology supports multi-port order reduction while assuring passivity of the resulting reduced network. We verify the proposed methodology on an LC voltage controlled oscillator implemented in CMOS technology and extracting parasitic resistances, capacitances, and inductances. Moreover we verify the proposed methodology on a memory design.