High-speed RF multi-modulus prescaler architecture for Σ-Δ fractional-N PLL frequency synthesizers

This paper describes the design of a multi-modulus prescaler for Σ-Δ fractional-N frequency-synthesizers. A new architecture is proposed to increase the critical time window for correct division. Quantification of the improvement of the architecture is done on the behavioral and transistor levels. The architecture is used to implement a multi-modulus prescaler with division factors 64-127 in a SiGe 0.35 μm BiCMOS technology with f_t of 60 GHz. The architecture improves the maximum operating frequency of the prescaler by 50%. Post layout simulations indicate that the prescaler can operate at an input frequency of 3.2 GHz while consuming only 6.4 mW, with a phase noise floor of -132 dBc/Hz, and up to 4.6 GHz while consuming 14 mW.