CMOS phase frequency detector for high speed applications

Author

Ismail, N.M.H. ; Othman, Masuri

Author_Institution

Inst. of MicroEngineering & Nanoelectron., Univ. Kebangsaan Malaysia (UKM), Bangi, Malaysia

fYear

2009

fDate

15-17 Nov. 2009

Firstpage

1

Lastpage

5

Abstract

A simple new phase frequency detector design is presented in this paper. Falling-edge PFD uses only 12 transistors and preserves the main characteristics of the conventional PFD. It is implemented using Silterra 0.18 Â¿m CMOS process. It consumes 6.6 Â¿W when operating at 50 MHz clock frequency with 1.8 V voltage supply. It has free dead zone and operates up to 2.5 GHz. It can be used in high speed and low power consumption applications. A single ended switch at source charge pump is presented as well. It is compatible with the FE-PFD outputs characteristics.

Keywords

CMOS integrated circuits; charge pump circuits; high-speed integrated circuits; integrated circuit design; low-power electronics; phase locked loops; Silterra 0.18 Â¿m CMOS process; charge pump; frequency 50 MHz; low power consumption; phase frequency detector; phase locked loop; transistors; voltage 1.8 V; Phase frequency detector; Charge Pump; High Speed Integrated Circuits; Phase Locked Loop; Phase frequency Detector;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Workshop (IDT), 2009 4th International

Conference_Location

Riyadh

Print_ISBN

978-1-4244-5748-9

Type

conf

DOI

10.1109/IDT.2009.5404165

Filename

5404165