Yield optimization by design centering and worst-case distance analysis

Author

Samudra, G.S. ; Chen, H.M. ; Chan, D.S.H. ; Ibrahim, Yaacob

Author_Institution

Center for Integrated Circuit Failure Anal. & Reliability, Nat. Univ. of Singapore, Singapore

fYear

1999

fDate

1999

Firstpage

289

Lastpage

290

Abstract

Process variations invariably give rise to a parametric yield below 100% for VLSI circuits. Improving the yield by choosing a set of optimum parameter values does not incur any extra cost, and it is a preferred method as it directly translates into profits. The paper presents an efficient and novel method to improve the VLSI parametric yield by selecting optimum parameter values. This method utilizes the worst-case distance analysis, design centering and gradient-dependent techniques. One circuit example is presented to demonstrate the optimization scheme

Keywords

SPICE; VLSI; circuit CAD; circuit optimisation; VLSI circuits; VLSI parametric yield; design centering; gradient-dependent techniques; optimization scheme; optimum parameter values; parametric yield; process variations; worst-case distance analysis; yield optimization; Circuit optimization; Circuit simulation; Cost function; Design engineering; Design optimization; Failure analysis; Robustness; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 1999. (ICCD '99) International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-0406-X

Type

conf

DOI

10.1109/ICCD.1999.808550

Filename

808550