Characteristics of the MFIS-FET structures processed using SBT ferroelectric thin films

Pt/SBT/TiO₂/Si and Pt/SBT/ZrO₂/Si structures were prepared for metal/ferroelectric/insulator/semiconductor field effect transistor (MFIS-FET) applications. After depositing TiO₂ or ZrO₂ films of 10-50 nm thickness by reactive sputtering on Si(100) substrates as buffer layers, SBT thin films of 400 nm thickness were prepared onto it using liquid source misted chemical deposition. Maximum capacitance of the Pt/SBT/TiO₂/Si and Pt/SBT/ZrO₂/Si structures increased with decreasing thickness of TiO₂ and ZrO₂ buffer layers. PVSBT/TiO₂ /Si and Pt/SBT/ZrO₂/Si structures exhibited a well-defined C-V hysteresis loop. Memory windows of the Pt/SBT(400 nm)/TiO₂(10 nm)/Si and Pt/SBT(400 nm)/ZrO₂(10 nm)/Si were 1.6 V and 0.72 V at 5 V, respectively