Delay optimization of CMOS logic circuits using closed-form expressions

CMOS remains the mainstream IC technology and optimization of digital CMOS circuits is a major focus of research. This paper presents a comprehensive model for estimation and optimization of the delay in submicron digital CMOS circuits. Our delay model for a logic gate depends on the topology of the gate, the size and topology of the preceding gate, and the load. This model is explicit in terms of the widths of the transistors and lead to closed-form formulas for optimization of digital CMOS gates. These formulas are simplified and approximated into rules of thumb for quick optimization and obtaining initial guess for running a CAD tool. Delay optimization of a critical path is performed by solving a set of non-linear transistor sizing formulas using iteration. Very good agreement is observed between the model and HSPICE simulations